1. Field of the Invention
The present invention is related to a computer readable medium comprising multiple instructions stored in a computer readable storage device, and more particularly, to a method for arranging dummy patterns and slot patterns in a semiconductor layout.
2. Description of the Prior Art
In recent years, the designing ruling of semiconductor device has become finer and finer, causing difficulties in controlling width and thickness of a pattern so that it has become harder and harder to overcome the bottleneck accompanied by the development of fabrication technology. When the fabrication technology of integrated circuit is developed to a degree under 130 nanometers, design for reliability/manufacturability (DfR/M) has become an important design factor. Accordingly, an original circuit layout designed by the circuit design engineer cannot be directly formed on a wafer but has to be modified by concerning the difficulties of the fabrication technology for producing a product that satisfies the electrical function of the original circuit design. Commonly, the well-known methods of design for reliability/manufacturability include adding virtual patterns, such as slot patterns or dummy patterns, in an original circuit layout to improve the problems of stress variation, iso-dense loading defect, or process uniformity.
However, the relative positions of the virtual patterns and the original circuit patterns have to be concerned when designing to add virtual patterns in a circuit layout. For example, the distance between one dummy pattern and the wire patterns in an iso region has to be in coordination with the spacing of wire patterns in a dense region for meeting the process uniformity requirement. Furthermore, in a case of adding a slot pattern into a circuit layout, the designer has to make sure that the slot disposed in a metal wide wire should have an enough distance from the contact holes in a lower or upper layer when the circuit layout is fabricated on a semiconductor device, such that the slot would not affect the electrical functions of the semiconductor device. As a result, when adding virtual patterns, whether the slot pattern or the dummy pattern, to an original circuit layout, there should be a minimum interval between the virtual patterns and the circuit patterns of the original circuit layout or some specific circuit patterns of another circuit layout stacked on top or bottom of the original circuit layout so as to avoid the virtual patterns affecting the performance of lithography of the circuit layout or the design of electrical function.
The method of adding dummy patterns according to the prior art is shown in FIG. 1, with the following steps:
Step 10: Provide an original circuit layout with at lest a circuit pattern.
Step 12: Add a dummy pattern group in the original circuit layout.
Step 14: Check and see whether the distance between each dummy pattern of the dummy pattern group and the circuit pattern is smaller than the minimum interval set according to the process conditions, and delete the dummy pattern when the distance is smaller than the minimum interval.
The method of step 12 of adding a dummy pattern group includes arranging pluralities of dummy patterns with a single coordinate system in the original circuit layout. For instance, an array of dummy patterns may be provided by taking the center of the original circuit layout as an origin of the coordinate system of the array. However, since the origin of the dummy pattern group is selected randomly according, it is unable to control the relative position of each dummy pattern and the circuit pattern so that it is likely that the dummy pattern have a distance from the circuit pattern smaller than the minimum interval and has to be deleted. As a result, only a few amounts of dummy patterns can be reserved, and therefore the effect of the dummy patterns disposed between the circuit patterns in the iso region is not obvious and cannot improve the of design for reliability/manufacturability.
Please refer to FIGS. 2-3, which are schematic diagrams of the method for adding dummy patterns in an original circuit layout according to the prior art. As shown in FIG. 2, an original circuit layout 20 is provided, comprising circuit patterns 22, 24 that are wire patterns. Referring to FIG. 3, point A is selected as an origin of a coordinate system of dummy patterns so that a group of dummy patterns 26 are added in the original circuit layout 20, which are arranged as an array. Sequentially, each of the dummy patterns 26 has to be compared with the circuit patterns 22, 24. If the distance between one dummy pattern 26 and the circuit pattern 22 or the circuit pattern 24 is smaller than the minimum interval DM, it has to be deleted. According to the prior art, since the origin point A of the coordinate system of the dummy patterns 26 is positioned at the left and bottom corner of the original circuit layout 20, the three columns of the dummy patterns 26 are leans to the circuit pattern 24 so that the distance between the circuit pattern 22 and the dummy patterns 26 in the second column is larger than the distance between the circuit pattern 24 and the dummy patterns 26 in the second column. As shown in FIG. 3, the distance D1 between the second column of the dummy patterns 26 and the circuit pattern 24 is smaller than the minimum interval DM, but the dummy patterns 26 in the first column or the third column overlap the circuit pattern 22 or the circuit pattern 24. Therefore, each of the dummy patterns 26 in the three columns has a spacing with the circuit pattern 22 or the circuit pattern 24 smaller than the minimum interval DM and has to be deleted, resulted in that no dummy patterns are remained in the final outputted circuit layout.
On the other hand, if the second column of the dummy patterns 26 is positioned in the middle of the spacing of the circuit pattern 22 and the circuit pattern 24, the distances of the dummy patterns 26 in the second column and the circuit pattern 22 or 24 should be larger than or equal to the minimum interval DM, such that the dumpy patterns 26 in the second column should be remained on the final outputted circuit layout, improving the fabrication performance of the semiconductor device. However, as mentioned above, since the origin point A of the coordinate system of the dummy patterns 26 is selected randomly, it is hard to control the relative positions between each dummy pattern 26 and the circuit patterns 22, 24. As a result, even though there is enough space for arranging the dummy patterns 26 between the circuit patterns 22, 24, all the dummy patterns 26 between the circuit patterns 22, 24 still have to be deleted according to the prior-art method for arranging virtual patterns, and no effective virtual patterns are remained on the circuit layout 20. Therefore, the problem of iso-dense loading defects or the design for reliability/manufacturability cannot be improved.
In order to solve the above-mentioned problem, Yamauchi et al. have proposed an U.S. Pat. No. 6,615,399 to disclose a method for arranging dummy patterns with multiple coordinate systems, whose method process is shown in FIG. 4:
Step 30: Provide an original circuit layout with at least a circuit pattern.
Step 32: Add a first dummy pattern group into the original circuit layout.
Step 34: Check to see whether the distance of each of the first dummy patterns of the first dummy pattern group and the circuit pattern is larger than or equal to the minimum interval? If yes, reserve the first dummy pattern and take it as an effective virtual pattern; otherwise, delete the dummy pattern not satisfying the minimum interval restriction.
Step 36: Add a second dummy pattern group into the original circuit layout.
Step 38: Check to see whether the distance between each of the second dummy patterns of the second dummy pattern group and each of the circuit pattern and the first dummy patterns reserved in step 36 is larger than or equal to the minimum interval? If yes, reserve the second dummy pattern; otherwise, delete the second dummy pattern not satisfying the minimum interval restriction.
Step 40: Add a third dummy pattern group into the original circuit layout.
Step 42: Check to see whether the distance between each of the third dummy patterns of the third dummy pattern group and each of the circuit pattern and the first and second dummy patterns reserved in steps 34, 38 is larger than or equal to the minimum interval? If yes, reserve the third dummy pattern; otherwise, delete the third dummy pattern not satisfying the minimum interval restriction.
Step 44: Combine the circuit pattern and the reserved first, second, and third dummy patterns to output the circuit layout.
Wherein, the step 36 of adding the second dummy pattern group is carried out by defining the second coordinate system as the first coordinate system of the first dummy pattern group shifted by a certain distance, and the step 40 is performed by shifting the coordinate system of the second dummy pattern group by a certain distance along the same direction in step 36 for adding the third dummy pattern group. Therefore, each dummy pattern of the first, second, and third dummy pattern groups are staggered on the circuit layout. To make short of the matter, Yamauchi et al. disclose a method for arranging dummy patterns that includes repeating the conventional method shown in FIG. 1 several times by shifting the coordinate systems of the dummy pattern group. However, according to this method, the total amount of dummy pattern groups and corresponding coordinate systems has to be decided before arranging the dummy patterns, and it still cannot insure that the remained dummy patterns reach the most permutable amount of dummy patterns even though two or more dummy pattern groups are provided. Furthermore, since several dummy patterns in different groups have to be arranged with various coordinate systems, each of which has to be compared with the circuit pattern and previously reserved dummy patterns, it cost much system resource and calculation time according to the method of Yamauchi et al.
As a result, it is still an important issue for the manufacturers to provide a more efficient method for arranging virtual patterns that can effectively control the positions of the virtual patterns so as to obtain the largest amount of the effective virtual patterns reserved in the final circuit layout.